FIXED-BIAS CONFIGURATION
The simplest of biasing arrangements for the n-channel JFET appears in Fig. 6.1. Referred
to as the fixed-bias configuration, it is one of the few FET configurations that
can be solved just as directly using either a mathematical or graphical approach. Both
methods are included in this section to demonstrate the difference between the two
philosophies and also to establish the fact that the same solution can be obtained using
either method.
The configuration of Fig. 6.1 includes the ac levels Vi and Vo and the coupling
capacitors (C1 and C2). Recall that the coupling capacitors are “open circuits” for the
dc analysis and low impedance (essentially short circuits) for the ac analysis. The
resistor RG is present to ensure that Vi appears at the input to the FET amplifier for
the ac analysis (Chapter 9). For the dc analysis,
IG ≅ 0 A
and VRG IGRG (0 A)RG 0 V

The zero-volt drop across RG permits replacing RG by a short-circuit equivalent, as
appearing in the network of Fig. 6.2 specifically redrawn for the dc analysis.











The fact that the negative terminal of the battery is connected directly to the defined
positive potential of VGS clearly reveals that the polarity of VGS is directly opposite
to that of VGG. Applying Kirchhoff’s voltage law in the clockwise direction of
the indicated loop of Fig. 6.2 will result in









Since VGG is a fixed dc supply, the voltage VGS is fixed in magnitude, resulting in the
notation “fixed-bias configuration.”
The resulting level of drain current ID is now controlled by Shockley’s equation:









Since VGS is a fixed quantity for this configuration, its magnitude and sign can
simply be substituted into Shockley’s equation and the resulting level of ID calculated.
This is one of the few instances in which a mathematical solution to a FET configuration
is quite direct.
A graphical analysis would require a plot of Shockley’s equation as shown in Fig.
6.3. Recall that choosing VGS VP/2 will result in a drain current of IDSS/4 when plotting
the equation.










SELF-BIAS CONFIGURATION

The self-bias configuration eliminates the need for two dc supplies. The controlling
gate-to-source voltage is now determined by the voltage across a resistor RS introduced
in the source leg of the configuration as shown in Fig. 6.8.







For the dc analysis, the capacitors can again be replaced by “open circuits” and
the resistor RG replaced by a short-circuit equivalent since IG 0 A. The result is the
network of Fig. 6.9 for the important dc analysis.
The current through RS is the source current IS, but IS ID and












VOLTAGE-DIVIDER BIASING

The voltage-divider bias arrangement applied to BJT transistor amplifiers is also applied
to FET amplifiers as demonstrated by Fig. 6.20. The basic construction is exactly
the same, but the dc analysis of each is quite different. IG 0 A for FET amplifiers,
but the magnitude of IB for common-emitter BJT amplifiers can affect the dc
levels of current and voltage in both the input and output circuits. Recall that IB provided
the link between input and output circuits for the BJT voltage-divider configuration
while VGS will do the same for the FET configuration.
The network of Fig. 6.20 is redrawn as shown in Fig. 6.21 for the dc analysis.
Note that all the capacitors, including the bypass capacitor CS, have been replaced by
an “open-circuit” equivalent. In addition, the source VDD was separated into two equiv-