BJT SMALL- SIGNAL ANALYSIS

COMMON-EMITTER FIXED-BIAS CONFIGURATION
The first configuration to be analyzed in detail is the common-emitter fixed-bias network of Fig. 8.1. Note that the input signal Vi is applied to the base of the transistor while the output Vo is off the collector. In addition, recognize that the input current Ii is not the base current but the source current, while the output current Io is the collector current. The small-signal ac analysis begins by removing the dc effects of VCC and replacing the dc blocking capacitors C1 and C2 by short circuit equivalents, resulting in the network of Fig. 8.2. Note in Fig. 8.2 that the common ground of the dc supply and the transistor emitter terminal permits the relocation of RB and RC in parallel with the input and output sections of the transistor, respectively. In addition, note the placement of the important network parameters Zi, Zo, Ii, and Io on the redrawn network. Substituting the re model for the common-emitter configuration of Fig. 8.2 will result in the network of Fig. 8.3.







































VOLTAGE-DIVIDER BIAS
The next configuration to be analyzed is the voltage-divider bias network of Fig.8.7.
Recall that the name of the configuration is a result of the voltage-divider bias at the input side to determine the dc level of VB.


















































CE EMITTER-BIAS CONFIGURATION
The networks examined in this section include an emitter resistor that may or may not be bypassed in the ac domain. We will first consider the unbypassed situation and
then modify the resulting equations for the bypassed configuration.


Unbypassed

The most fundamental of unbypassed configurations appears in Fig. 8.10. The re equivalent model is substituted in Fig. 8.11, but note the absence of the resistance ro.The effect of ro is to make the analysis a great deal more complicated, and considering the fact that in most situations its effect can be ignored, it will not be included in the current analysis. However, the effect of ro will be discussed later in this section.Applying Kirchhoff’s voltage law to the input side of Fig. 8.11 will result in