COMPOUND CONFIGURATION

The cascode is a two-stage amplifier composed of a transconductance amplifier followed by a current buffer. Compared to a single amplifier stage, this combination may have one or more of the following advantages: higher input-output isolation, higher input impedance, higher output impedance, higher gain or higher bandwidth. In modern circuits, the cascode is often constructed from two transistors (BJTs or FETs), with one operating as a common emitter or common source and the other as a common base or common gate. The cascode improves input-output isolation (or reverse transmission) as there is no direct coupling from the output to input. This eliminates the Miller effect and thus contributes to a much higher bandwidth.



Figure 1: N-channel cascode amplifier with resistive load (neglecting biasing details)

Figure 1 shows an example of cascode amplifier with a common source amplifier as input stage driven by signal source V_in. This input stage drives a common gate amplifier as output stage, with output signal V_out.

The major advantage of this circuit arrangement stems from the placement of the upper Field Effect Transistor (FET) as the load of the input (lower) FET's output terminal (drain). Because at operating frequencies the upper FET's gate is effectively grounded, the upper FET's source voltage (and therefore the input transistor's drain) is held at nearly constant voltage during operation. In other words, the upper FET exhibits a low input resistance to the lower FET, making the voltage gain of the lower FET very small, which dramatically reduces the Miller feedback capacitance from the lower FET's drain to gate. This loss of voltage gain is recovered by the upper FET. Thus, the upper transistor permits the lower FET to operate with minimum negative (Miller) feedback, improving its bandwidth.

The upper FET gate is electrically grounded, so charge and discharge of stray capacitance C_dg between drain and gate is simply through R_D and the output load (say R_out), and the frequency response is affected only for frequencies above the associated RC time constant: τ = C_dg R_D//R_out, namely f = 1/(2πτ), a rather high frequency because C_dg is small. That is, the upper FET gate does not suffer from Miller amplification of C_dg.

If the upper FET stage were operated alone using its source as input node (i.e. common-gate (CG) configuration), it would have good voltage gain and wide bandwidth. However, its low input impedance would limit its usefulness to very low impedance voltage drivers. Adding the lower FET results in a high input impedance, allowing the cascode stage to be driven by a high impedance source.

If one were to replace the upper FET with a typical inductive/resistive load, and take the output from the input transistor's drain (i.e. a common-emitter (CE) configuration), the CE configuration would offer the same input impedance as the cascode, but the cascode configuration would offer a potentially greater gain and much greater bandwidth.

Figure 2: BJT Cascode using ideal current sources for DC bias and large coupling capacitors to ground and to the AC signal source; capacitors are short circuits for AC.

BJT Cascode: low-frequency small-signal parameters^[3]

The idealized small-signal equivalent circuit can be constructed for the circuit in figure 2 by replacing the current sources with open-circuits and the capacitors with short circuits, assuming they are large enough to act as short-circuits at the frequencies of interest. The BJTs can be represented in the small-signal circuit by the hybrid-pi model.

	Definition	Expression
Voltage gain
Input resistance		rπ2
Output resistance

MOSFET Cascode: low-frequency small-signal parameters^[4]

Similarly the small-signal parameters can be derived for the MOSFET version, also replacing the MOSFET by its hybrid-pi model equivalent. This derivation can be simplified by noting that the MOSFET gate current is zero, so the small-signal model for the BJT becomes that of the MOSFET in the limit of zero base current:

,

Figure 3: MOSFET Cascode using ideal voltage sources for DC gate bias and a DC current source as active load

where V_T is the thermal voltage.

	Definition	Expression
Voltage gain		− (gm1rO1 + 1)gm2rO2
Input resistance
Output resistance

The combination of factors g_mr_O occurs often in the above formulas, inviting further examination. For the bipolar transistor this product is (see hybrid-pi model):

.

In a typical discrete bipolar device the Early voltage V_A ≈ 100 V and the thermal voltage near room temperature is V_T ≈ 25 mV, making g_mr_O ≈ 4000, a rather large number. From the article on hybrid-pi model, we find for the MOSFET in the active mode:

At the 65 nanometer technology node, I_D ≈ 1.2 mA/μ of width, supply voltage is V_DD = 1.1 V; V_th ≈ 165 mV, and V_ov = V_GS-V_th ≈ 5%V_DD ≈ 55 mV. Taking a typical length as twice the minimum, L = 2 L_min = 0.130 μm and a typical value of λ ≈ 1/(4 V/μm L), we find 1/λ ≈ 2 V, and g_mr_O ≈ 110, still a large value.^{[5] [6]} The point is that because g_mr_O is large almost regardless of the technology, the tabulated gain and the output resistance for both the MOSFET and the bipolar cascode are very large. That fact has implications in the discussion that follows.